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ics854s054agi revision a september 28, 2012 1 ?2012 integrated device technology, inc. data sheet 4:1 differential-to-lvds clock multiplexer ICS854S054I sel0 sel1 pclk0 npclk0 pclk1 npclk1 pclk2 npclk2 pclk3 npclk3 q nq 00 (default) 01 10 11 pulldown pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown pulldown pullup/pulldown pulldown pulldown 1 2 3 4 5 6 7 8 v dd q nq gnd npclk3 pclk3 npclk2 pclk2 16 15 14 13 12 11 10 9 pclk0 npclk0 pclk1 npclk1 v dd sel0 sel1 gnd general description the ICS854S054I is a 4:1 differential-to-lvds clock multiplexer which can operate up to 2.5ghz. the ICS854S054I has 4 selectable differential clock inputs. the pclk, npclk input pairs can accept lvpecl, lvds or cml levels. the fu lly differential ar chitecture and low propagation delay make it ideal for use in clock distribution circuits. the select pins have internal pulldown resistors. the sel1 pin is the most significant bit and the binary number applied to the select pins will select the same nu mbered data input (i.e., 00 selects pclk0, npclk0). features ? high speed 4:1 differential multiplexer ? one differential lvds output pair ? four selectable differential pclk, npclk input pairs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml ? maximum output frequency: 2.5ghz ? translates any single ended input signal to lvds levels with resistor bias on npclkx input ? additive phase jitter, rms: 0.147ps (typical) ? part-to-part skew: 300ps (maximum) ? propagation delay: 700ps (maximum) ? supply voltage range: 3.135v to 3.465v ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package pin assignment block diagram ICS854S054I 16-lead tssop 5.0mm x 4.4mm x 0.92mm package body g package top view
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 2 ?2012 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics table 3. clock input function table number name type description 1 pclk0 input pulldown non-inverting differential clock input. 2 npclk0 input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 3 pclk1 input pulldown non-inverting differential clock input. 4 npclk1 input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 5, 16 v dd power positive supply pins. 6, 7 sel0, sel1 input pulldown clock select in put pins. lvcmos/lvttl interface levels. 9 pclk2 input pulldown non-inverting differential clock input. 10 npclk2 input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 11 pclk3 input pulldown non-inverting differential clock input. 12 npclk3 input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 8, 13 gnd power power supply ground. 14, 15 nq, q output differential output pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown pulldown resistor 75 k ? r vdd /2 rpullup/pulldown resistor 50 k ? inputs outputs sel1 sel0 q nq 0 0 pclk0 npclk0 0 1 pclk1 npclk1 1 0 pclk2 npclk2 1 1 pclk3 npclk3
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 3 ?2012 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4c. differential lvpec l input dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ja 100c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 57 68 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current sel[1:0] v dd = v in = 3.465v 150 a i il input low current sel[1:0] v dd = 3.465v, v in = 0v -10 a symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk[0:3], npclk[0:3] v dd = v in = 3.465v 150 a i il input low current pclk[0:3] v dd = 3.465v, v in = 0v -10 a npclk[0:3] v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage 0.15 1.2 v v cmr common mode input voltage; note 1 gnd + 1.2 v dd v
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 4 ?2012 integrated device technology, inc. table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. all parameters measured 1.0ghz unless noted otherwise. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs on different devices o perating at the same supply voltage , same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. note 3: this parameter is defined in accordance with jedec standard 65. note 4: q, nq output measured differentially. see parameter measurement information for mux isolation diagram. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 380 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.28 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units f out output frequency 2.5 ghz t pd propagation delay; note 1 295 470 700 ps t jit(?) buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.147 ps tsk (pp) part-to-part skew; note 2, 3 300 ps tsk (i) input skew 10 50 ps t r / t f output rise/fall time 20% to 80% 70 150 250 ps mux isolation mux isolation; note 4 155.52mhz, v pp = 800mv 86 db
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 5 ?2012 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamen tal frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device me ets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. measured using a rohde & schwarz sma100 as the input source. ssb phase noise dbc/hz offset from carrier frequency (hz)
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 6 ?2012 integrated device technology, inc. parameter measureme nt information 3.3v output load ac test circuit propagation delay input skew differential input level part-to-part skew mux isolation scope qx nqx 3.3v5% power supply +? float gnd v dd t pd nq q npclk[0:3] pclk[0:3] t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) nq q npclkx pclkx pclkx pclky npclky v cmr cross points v pp v dd gnd npclk[0:3] pclk[0:3] t sk(pp) part 1 part 2 nq q nq q amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 7 ?2012 integrated device technology, inc. parameter measurement in formation, continued output rise/fall time offset voltage setup differential output voltage setup 20% 80% 80% 20% t r t f v od nq q out out lvds dc input ? v os / ? v os v dd 100 out out dc input v dd lvds
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 8 ?2012 integrated device technology, inc. applications information recommendations for unused input pins inputs: pclk/npclk inputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requi res that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r2 1k r1 1k c1 0.1uf ro + rs = zo v1 vc c vc c
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 9 ?2012 integrated device technology, inc. 3.3v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds, cml and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 2a. pclk/npclk inpu t driven by a cml driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by a 3.3v lvds driver figure 2b. pclk/npclk input driven by a built-in pullup cml driver figure 2d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple pclk npclk lvpecl input cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 ? r2 50 ? r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? pclk npclk 3.3v 3.3v lvpecl lvpecl input 3.3v r1 100 ? lvds pclk npclk 3.3v lvpecl input zo = 50 ? zo = 50 ? 3.3v r1 100 ? cml built-in pullup pclk npclk 3.3v lvpecl input zo = 50 ? zo = 50 ? r3 84 r4 84 r1 125 r2 125 r5 100 - 200 r6 100 - 200 pclk npclk 3.3v lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v lvpecl input c1 c2
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 10 ?2012 integrated device technology, inc. lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an op tional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o z t z o z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 11 ?2012 integrated device technology, inc. lvds power considerations this section provides information on power dissipa tion and junction temperature for the ICS854S054I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854S054I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * i dd_max = 3.465v * 68ma = 235.62mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.236w * 100c/w = 108.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 100c/w 9 4.2c/w 90.2c/w
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 12 ?2012 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ICS854S054I is: 450 this device is pin and function compatible , and a suggested replacement for ics854054i. package outline and package dimensions package outline - g suffix for 16 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 100c/w 94.2c/w 90.2c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer ics854s054agi revision a september 28, 2012 13 ?2012 integrated device technology, inc. ordering information table 9. ordering information part/order number marking package shipping packaging temperature 854s054agilf 4s054ail ?lead-free? 16 lead tssop tube -40 c to 85 c 854s054agilft 4s054ail ?lead-free? 16 lead tssop tape & reel -40 c to 85 c
ICS854S054I data sheet 4:1, differential-to-lvds clock multiplexer disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discre tion. all information in this document, including descriptions of product features a nd performance, is subject to change wit hout notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of a ny kind, whether express or implie d, including, but not limited to, the suitability of idt?s products for any par ticular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reas onably expected to signif- icantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the id t logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, ar e the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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